Navigating the Future: PCIe Gen6 and Data Transfer

 

Alphawave’s Role in Advancing PCIe Gen6

Together with Key sight, a manufacturer of testing and verification equipment, Alphawave, a contract chip designer and provider of silicon intellectual property, demonstrated this month the interoperability of its PCIe 6.0 controller and physical interface with Key sight’s testing equipment at a data transfer rate of 64 GT/s. By taking this step, Alphawave is demonstrating that they are prepared to produce chips with a PCIe 6.0 interface and are joining an increasing number of businesses that are laying the groundwork for the arrival of the first PCIe 6.0 devices in the market in 2024.

IP provider Synopsys has been selling its PCIe 6.0 IP package, which includes a controller and physical interface (PHY), since 2021. The company showed earlier this year that its PCIe Gen6 solution is compatible with Intel’s test chip.

The silicon implementation of a PCIe 6.0 64 GT/s interface by Alphawave supports the industry’s first CXL 2.0 protocol in addition to operating at full speed with pulse amplitude modulation with four levels (PAM4) signaling with Keysight’s Protocol Exerciser. Additionally, the implementation fully supports FLIT mode, PCIe Gen6’s Forward Error Correction (FEC), and other new interconnection standard features. Moreover, the CXL 3.0 protocol allows for additional expansion of this PCIe Gen6 platform.

Letizia Giuliano, Vice President of IP Product Marketing at Alphawave Semi, stated, “Test and measurement are critical aspects of interoperability, enabling Alphawave Semi to bring our products and customer solutions to market faster.” “We are excited about our collaboration with Key sight, which speeds up the transition to 64 GT/s through Key sight’s state-of-the-art PCIe 6.0 protocol validation solution and instills confidence in their ability to consistently provide connectivity solutions that accelerate AI processing in high-performance computing and data infrastructure.”

PCI Express 6.0 Specification

Features of the PCIe 6.0 Specification

• 64 GT/s raw data rate with an x16 configuration that can reach 256 GB/s
• Pulse Amplitude Modulation (PAM4) with four levels of signaling, leveraging PAM4 that is currently in use in the market
• Cyclic Redundancy Check (CRC) and Lightweight Forward Error Correct (FEC) reduce the bit error rate increase linked to PAM4 signaling.
• Double the bandwidth gain is possible with Flit (flow control unit) based encoding, which also supports PAM4 modulation and cooperates with the FEC and CRC.
• Flit Mode’s updated packet layout adds functionality and streamlines processing.
• Keeps backwards compatibility with all PCIe technology generations prior.

The main target market for Synopsys’ IP and technology licenses is large chip designers. In contrast, smaller businesses that typically do not design or implement intellectual property themselves can hire Alphawave to develop custom chips or license technologies. The company states that its PCIe subsystem ‘has been built off the industry’s most successful PAM4 SerDes IP,’ and that it offers low latency and extreme power efficiency.’ Moreover, the CXL 3.0 protocol allows for additional expansion of this PCIe Gen6 platform.