SK hynix’s 4D NAND Innovations
SK Hynix introduced 300-layer NAND flash memory. After introducing its first 96-layer solution in 2018, SK hynix’s 321-layer 1 Tb TLC 4D NAND smashed records again. The company’s 4D NAND technology integrates chip size reduction, layer growth, reliability, and productivity innovations.
This Tech Pathfinder episode introduces 4D NAND from SK Hynix. 4D stacking innovations such Cost-Effective 3-Plug arrangement, Sideway Source, All Peri. Under Cell (PUC), and Advanced Charge Trap Flash boost performance. Multi-Site Cell (4D NAND) technologies that avoid stacking will also be discussed.
- Cell-control peripheral.
NAND Flash Memory Basics
To understand 4D NAND technology, master its basics and language.
The smallest data storage unit is cells. NAND flash memory has floating and control gates. When voltage is supplied, the control gate stores electrons along the floating gate route. The floating gate electrons identify NAND memory cells as 0 or 1. Cell electrons determine this. Cells with few electrons are 0, while those with many are 1.
The number of bits per cell classifies 4D NAND flash memory. These include 1-bit, 2-bit, 3-bit, 4-bit, and 5-bit cells. Giga and tera are NAND flash memory capacities. A 1 Tb TLC NAND flash device includes 330 billion 3-bit cells.
4D chip size is reduced by cell stacking.
SK Hynix makes high-capacity NAND storage using four 4D NAND technologies.
Affordable 3-Plug Formation
In semiconductor technology, cost efficiency is a priority. Stack more cells and build as many chips as possible on a wafer to reduce chip size. Inefficiently stacking substrates and repeating cell fabrication for each layer raises manufacturing expenses. There are many substrate layers, vertical holes called plugs are drilled, and cells are generated next to them.
Since present etching equipment can only etch 100 layers at once, creating plugs to the bottom layer becomes tougher with more layers. In order to create a NAND flash product with over 300 layers, stack 100 layers and plug etch three times. SK hynix’s Cost-Effective 3-Plug formation allows simultaneous cell production on all layers.
In one process, SK Hynix created word lines, word line steps, and electron tunnels. The business launched the highest-density 321-layer 4D NAND at affordable cost in August 2023.
- Word lines: Each NAND cell layer’s control gate binding structure.
- Word line staircases: Showcase each layer’s word line.
Sideways source
Semiconductor plugs carry electrons. Inside a plug, CTF film covers this passage. Remove CTF film where the connector and NAND flash layer bottom meet to interconnect two pathways. Plug to NAND flash layer bottom (channel and source line) via sideway source. The bottom CTF coating was vertically removed with etching gas from the plug’s top. Inlaying multiple plugs did not align their centers. This prevented the etching gas from reaching the bottom, breaking the plug’s cell-side CTF coating.
- CTF film: An oxide-nitride floating gate replacement.
An inside plug channel stores the source line at the bottom of a NAND layer. As source line electrons ascend the channel to the NAND layer, floating gates store them.
SK Hynix replaced the vertical connector with a horizontal one. The etching gas is fed into a separate conduit to reach the NAND layer bottom and remove the CTF coating on both plug sides.
Sideways Source injects etching gas into the plug indirectly. Thus, misplaced plugs do not damage the interior. Therefore, SK hynix has reduced defects, increased production, and eliminated the multiple stacking cost issue.
SK hynix has optimized its horizontal pathway connections to prevent bottom voids since debuting 4D NAND in 2018. This improved 238-layer NAND flash memory production efficiency by 34% over the 176-layer product and solidified its market leadership with its 321-layer NAND.
Complete PUC
PUC enhances stacks and reduces chip size by putting the peripheral circuit (peri.) under the cell. The initial 4D NAND flash structure and commercial development were made possible by PUC. All firm PUC technology shrinks the peri. to match the cell or fit smaller cells. To improve technology, SK Hynix is miniaturizing the peri. by reducing transistor size and number and moving it under the cell.
SK Hynix’s 238-layer 512 Gb TLC NAND pioneered this method. The company reduced chip and peri. size by over 30% compared to the previous generation to improve production efficiency and cost competitiveness. For smaller micro. and chips, SK Hynix will improve its understanding and technology.
Charge Trap Flash improves
More electrons are retained by advanced CTF, decreasing data degradation. CTF stores electrons in nonconductors, not floating gates. Thus, CTF switched electron storing to nonconductors to reduce conductor inter-cell interference. Nonconductors lose electrons due to unstable CTF material (nitrogen-silicon compound) vacancies. Electrons at unstable regions quickly break bonds and are ejected, losing info.
- Device miniaturization corrupts data by interfering with adjacent cell electrons.
SK Hynix protects unstable areas with hydrogen to prevent electrons from entering its Advanced CTF and increases binding agents to store electrons. Advanced CTF reduces escaped electrons to increase electron storage. Improved electron count, read error, and latency estimation.
NAND flashes with little electrons make mistakes recognizing data. The SLC flash memory recognizes data with 10 electrons as 0, 1 to 5 as 0, and 6 to 10 as 1. Five escaping electrons contaminate data treated as 1 and cause an error. As cells become MLC and higher, this problem arises.
TLC classifies eight states from 000 to 111. The 10 electrons distinguish each state by one or two electrons. This varies substantially from SLC, which assigns five electrons per state. Even a few electrons can ruin data.
In contrast, Advanced CTF distinguished 100-electron data. Data is 0 for 0–50 electrons and 1 for 51–100. Even if some electrons escape, the large number reduces data misinterpretation. Reduced errors speed up reading.
Advanced CTF increased SK Hynix’s 176-layer NAND solution’s electron count determination by 25%. Advanced CTF-based memory systems reduce latency for quick data processing in gaming and automotive applications.
4D helps improve performance and density by increasing horizontal cell density and stacking.
Each layer raises semiconductor memory fabrication costs. Cost reduction is no longer possible because adding bits above TLC raises costs. To boost storage capacity and cost, SK Hynix is developing 4D technology to increase cell layers and horizontal density. By improving structure, 4D Multi Site Cell (MSC) boosts horizontal density and bit count.
MSC Multisite Cell
Horizontally raising cell density has two approaches. Multi-level cell (MLC) technology divides electron counts to fit more bits in a cell. Affects SLC-QLC NAND flashes. Second, MSC technology improves cell electron storage sites, allowing them to retain more information.
MLC technology is sold in 4-bit QLC systems, but 5-bit PLC and above performance and reliability are tough. This is due to electron count restrictions.
An MLC 6-bit hexa-level cell (HLC) must store 64 states from 000000 to 111111. Lacking electrons to identify each state makes this error-prone and time-consuming. Electron counting is four times poorer than 4-bit QLC.
MSC-based HLCs multiply eight states from 000 to 111 in two spaces to 64 data storage states. Electron count difference doubles from 4-bit QLC. Therefore, it has HLC capacity but TLC speed. SK hynix claims 20-fold faster MSC read/write speeds. MSC’s great capacity, speed, and durability make SK hynix NAND flash the perfect choice for future multimodal AI.
- 5-bit normal cell vs. 2.5-bit x 2.5-bit MSC.
- Multimodal AI: picture, audio, and text processing.
Fixing Industry Issues for Future
In this last Tech Pathfinder episode, SK hynix demonstrated how 4D NAND can solve industry issues now and in the future. The company’s 4D NAND flash products have higher performance and cost and will exceed stacking limits.
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