AMD Alveo UL3524
Today’s top trading firms, market makers, hedge funds, brokerages, and exchanges compete for low-latency trade execution in complicated algorithmic trading, pre-trade risk assessment, and real-time market data delivery.
Achieving a minimal actional latency of 13.9 nanoseconds (ns) for trade execution, AMD, in partnership with Exegy, a global pioneer in advanced trading and execution systems, has set a world record for the STAC-T0 test. This is the fastest recorded STAC-T0 benchmark result to date and leads to a decrease of up to 49% in tick-to-trade latency when compared to the previous record. Prior top speed of up to 24.2 ns was also achieved by reference design with AMD accelerators.
With an emphasis on ultra-low latency electronic trading applications, AMD asked STAC to evaluate the AMD Alveo UL3524 FPGA Accelerator’s performance using STAC-T0 benchmarks.
The AMD Alveo UL3524 FPGA Accelerator on a Dell PowerEdge R7525 server with AMD EPYC 7313 processors housed the Exegy nxFramework and Exegy IP Core nxTCP-UDP-10g-ULL, which made up the stack.
When evaluating products that allow for quick analyses of time-series tick data, STAC benchmarks are the accepted industry standard. Regardless of whether a trading platform uses FPGAs, CPUs and software, or other hardware, STAC-T0 measures the tick-to-trade network-I/O latency of any platform with remarkable accuracy. The most important statistic in STAC-T0 is Actionable Latency, which is defined as the interval between the first bit of the simulated outgoing order and the last bit of incoming data required to make a trading decision.
AMD EPYC 7313
A Dell PowerEdge R7525 server with AMD EPYC 7313 processors, an Arista 7130 platform, and an Arista MetaWatch 7130 device were used to run the Exegy nxFramework and Exegy nxTCP-UDP-10g-ULL IP Core on the AMD Alveo UL3524 accelerator card, a FinTech card designed specifically for fast trade execution and powered by an AMD Virtex UltraScale+ FPGA.
With 1,680 DSP slices of computing, 780K LUTs of FPGA fabric, and a revolutionary transceiver architecture, the AMD Alveo UL3524 accelerator is a powerful tool. It is intended to speed up proprietary trading algorithms in hardware, allowing traders to customise their designs for proprietary algorithms and trading methods powered by artificial intelligence.
According to Girish Malipeddi, Director of Product Marketing at AMD’s AECG-Data Centre, “a nanosecond can determine the difference between a profitable or losing trade in ultra-low latency trading.” “This benchmark displays independently measured, validated, real-world outcomes that demonstrate how AMD is expanding the possibilities and limits in high-speed trading and financial technologies overall.”
To execute the requirements of the STAC-T0 benchmark on the Alveo UL3524 card, Exegy supplied the application, which included the required FPGA IP and related software.
Director of FPGA solutions at Exegy Olivier Cousin stated, “Exegy and AMD are thrilled to have set a record for the tick-to-trade latency with the completion of this latest STAC-T0 benchmark.” “The best published results to date are achieved by this year’s STAC-T0, which combines the new ultra-low latency TCP-UDP IP stack with Exegy’s FPGA programming framework.”
Overview
Quick Trade Response
The Virtex UltraScale+ FPGA, designed specifically for electronic trading, powers the Alveo UL3524. With a transceiver architecture that is revolutionary, the device may achieve a latency of less than 3 ns for world-class trade execution. This results in 7X better performance than existing FPGA technology.
Intended for Ultra-Low Latency (ULL) Operation
Deterministic trade execution with transceiver delay of less than 3 ns for optimal performance
AI-Powered Trading Strategies and Personalised Algorithms
Using both open-source PyTorch development flows and conventional FPGA design, developers may include low latency AI models into trading systems.
For a Wide Range of Fintech Uses
Hardware acceleration for pre-trade risk assessment, market data delivery, and algorithmic trading
Adaptability of Hardware
The AMD Alveo UL3524 accelerator card is designed to accelerate proprietary trading algorithms in hardware, allowing traders to adapt their design to changing market conditions and strategies. It has 64 ultra-low latency transceivers, 780K LUTs of FPGA fabric, and 1,680 DSP slices of computing.
For conventional FPGA flows, the Vivado Design Suite is compatible with the AMD Alveo UL3524 accelerator card. Additionally, AMD is making the open-source, community-supported FINN development framework available to developers, allowing the integration of low-latency AI models into high-performance trading platforms.
A competitive edge in the financial markets
The AMD Alveo UL3524 accelerator can be used by brokerages, data vendors, market makers, hedge funds, proprietary trading businesses, and more for pre-trade risk management, market data distribution, and ULL algorithmic trading. High performance and determinism are guaranteed across a wide range of use cases by the convergence of low latency networking, FPGA flexibility, and hardware acceleration.
Algorithmic Trading ULL
Market-making services to intricate algorithmic trading.
Risk Management Prior to Trade
Assess pre-trade risk and ensure regulatory compliance with extremely low latency.
Supply of Market Data
Deliver dependable real-time market data to exchanges and brokerages.
“A Dell PowerEdge R7525 server with AMD EPYC 7313 processors running Exegy nxFramework and Exegy IP Core nxTCP-UDP-10g-ULL on an AMD Alveo UL3524 FPGA Accelerator.” Configure the system to test: A Dell PowerEdge R7525 server with AMD EPYC 7313 processors and an Arista 7130 platform with a MetaWatch 7130 device, running the STAC-T0 benchmark test, is equipped with an AMD Alveo UL3524 accelerator card that is powered by an AMD Virtex Ultrascale+ FPGA.
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